T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
{"title":"浮动体RAM技术及其32nm及以上节点的可扩展性","authors":"T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama","doi":"10.1109/IEDM.2006.346846","DOIUrl":null,"url":null,"abstract":"Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"Floating Body RAM Technology and its Scalability to 32nm Node and Beyond\",\"authors\":\"T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama\",\"doi\":\"10.1109/IEDM.2006.346846\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant\",\"PeriodicalId\":366359,\"journal\":{\"name\":\"2006 International Electron Devices Meeting\",\"volume\":\"100 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2006.346846\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
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