一种采用源侧热电子注入的封装控制栅极结构的新型2位/单元MONOS存储器件

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015454

H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi

{"title":"一种采用源侧热电子注入的封装控制栅极结构的新型2位/单元MONOS存储器件","authors":"H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi","doi":"10.1109/VLSIT.2002.1015454","DOIUrl":null,"url":null,"abstract":"We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection\",\"authors\":\"H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi\",\"doi\":\"10.1109/VLSIT.2002.1015454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

我们提出了一种新颖的2位/单元MONOS存储器结构，其特点是封装门。编程和擦除分别采用源侧热电子注入和热空穴注入。实现了编程速度<1 /spl mu/s，编程电流<2 /spl mu/ a //spl mu/m，擦除速度<10 /spl mu/s。

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A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection

We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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