一种预测晶圆级晶片级封装应力对高精度电路影响的方法

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI:10.1109/IEDM.2015.7409646

R. van Dalen, H. P. Tuinhout, M. Stoutjesdijk, J. van Zwol, J. J. M. Zaal, J. H. J. Janssen, F. H. M. Swartjes, P. A. M. Bastiaansen, M. C. Lammers, L. Brusamarello, M. Stekelenburg

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引用次数: 9

摘要

提出了一种方法，可以定量预测WLCSP引起的机械应力对高精度混合信号集成电路的影响。利用专用测试芯片上测量的高分辨率实验变异性数据对模拟流程进行了调整。该方法以一个受WLCSP应力诱发变异性影响的片上振荡器电路为例。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits

A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.

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2015 IEEE International Electron Devices Meeting (IEDM)

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