Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba
{"title":"坚固的晶圆薄化至2.6 μm,适用于无凹凸互连和DRAM WOW应用","authors":"Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba","doi":"10.1109/IEDM.2015.7409653","DOIUrl":null,"url":null,"abstract":"An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications\",\"authors\":\"Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba\",\"doi\":\"10.1109/IEDM.2015.7409653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.\",\"PeriodicalId\":336637,\"journal\":{\"name\":\"2015 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"91 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2015.7409653\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2015.7409653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications
An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.