L. Bera, H. Nguyen, N. Singh, T. Liow, D.X. Huang, K. Hoe, C. Tung, W. Fang, S. Rustagi, Y. Jiang, G. Lo, N. Balasubramanian, D. Kwong
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Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated
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