Modeling and testing comparison faults for ternary content addressable memories

This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations to cover 100% comparison faults for an N /spl times/ B-bit TCAM. Compared with the previous work, the proposed test algorithm has lower time complexity for TCAMs with wide words and the time complexity is independent of the number of stuck-on faults. Also, the algorithm can cover all defects that cause a failed Compare operation. Moreover, it can be realized by built-in self-test circuitry with lower area cost.