Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention

We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude