长码长的高吞吐量LDPC解码器

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI:10.1109/VDAT.2006.258134

T. Ishikawa, K. Shimizu, T. Ikenaga, S. Goto

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引用次数: 3

摘要

我们设计并实现了采用内存缩减方法的LDPC解码器，以实现长码长的高吞吐量和实用的硬件尺寸。该解码器使用改进的最小和算法解码(3,6)-11520位的正则LDPC码。该解码器在69 MHz的工作频率下实现了312 Mb/s的吞吐量，并进行了20次迭代解码。登机门数为2M

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High-Throughput LDPC Decoder for Long Code-Length

We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates

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2006 International Symposium on VLSI Design, Automation and Test

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