存储器嵌入逻辑lsi的可测试性设计方法

Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI:10.1109/ATS.1992.224406

K. Hatayama, T. Hayashi, M. Takakura, T. Suzuki, S. Michishita, H. Satoh

{"title":"存储器嵌入逻辑lsi的可测试性设计方法","authors":"K. Hatayama, T. Hayashi, M. Takakura, T. Suzuki, S. Michishita, H. Satoh","doi":"10.1109/ATS.1992.224406","DOIUrl":null,"url":null,"abstract":"The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An approach to design-for-testability for memory embedding logic LSIs\",\"authors\":\"K. Hatayama, T. Hayashi, M. Takakura, T. Suzuki, S. Michishita, H. Satoh\",\"doi\":\"10.1109/ATS.1992.224406\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224406\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224406","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

作者提出了一种嵌入随机存取存储器(ram)的逻辑lsi的可测试性设计方法。这种方法使用可扫描ram来增强ram本身及其外围电路的可测试性。自动测试生成既适用于ram，也适用于整个逻辑电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An approach to design-for-testability for memory embedding logic LSIs

The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit.<>

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Proceedings First Asian Test Symposium (ATS `92)

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