{"title":"具有检查序列的易于测试的顺序电路的合成","authors":"S. Shibatani, K. Kinoshita","doi":"10.1109/ATS.1992.224408","DOIUrl":null,"url":null,"abstract":"A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Synthesis of easily testable sequential circuits with checking sequences\",\"authors\":\"S. Shibatani, K. Kinoshita\",\"doi\":\"10.1109/ATS.1992.224408\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224408\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224408","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Synthesis of easily testable sequential circuits with checking sequences
A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown.<>
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