基于射频信道的高速数字总线设计与优化

2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2022-10-09 DOI:10.1109/EPEPS53828.2022.9947153

Nikhita Baladari, R. Wenzel

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引用次数: 0

摘要

将高速数字电子器件和高频雷达信道集成在一个层数有限的封装中，可能导致返回路径受损和信号完整性降低。在本文中，我们设计了一个77 GHz射频信道上的数字模块，并使用不同的封装模型来评估数字模块和射频模块之间的数字耦合及其对信号完整性的影响。

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Design and Optimization of High-Speed Digital Bus Over RF Channel

Integration of high-speed digital electronics and high-frequency radar channels in a package with limited layers can result in compromised return paths and degraded signal integrity. In this paper, we designed a digital block over a 77 GHz RF channel and used different package models to evaluate the digital coupling between the digital and RF blocks and the effect on their signal integrity.

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2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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