S.S. Chung, S.-J. Chen, C.K. Yang, S.M. Cheng, S.H. Lin, Y.C. Sheng, H. Lin, K.-T. Hung, D.Y. Wu, T. Yew, S. Chien, F. Liou, F. Wen
{"title":"采用直接隧道模式(12/spl sim/ 16a)栅极氧化物,对亚100nm CMOS器件的界面陷阱进行了新的直接测定","authors":"S.S. Chung, S.-J. Chen, C.K. Yang, S.M. Cheng, S.H. Lin, Y.C. Sheng, H. Lin, K.-T. Hung, D.Y. Wu, T. Yew, S. Chien, F. Liou, F. Wen","doi":"10.1109/VLSIT.2002.1015394","DOIUrl":null,"url":null,"abstract":"For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16 A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various rapid thermal nitric oxide (RTNO) grown and remote plasma nitridation (RPN) treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"73 6 Suppl 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide\",\"authors\":\"S.S. Chung, S.-J. Chen, C.K. Yang, S.M. Cheng, S.H. Lin, Y.C. Sheng, H. Lin, K.-T. Hung, D.Y. Wu, T. Yew, S. Chien, F. Liou, F. Wen\",\"doi\":\"10.1109/VLSIT.2002.1015394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16 A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various rapid thermal nitric oxide (RTNO) grown and remote plasma nitridation (RPN) treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"73 6 Suppl 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16 A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various rapid thermal nitric oxide (RTNO) grown and remote plasma nitridation (RPN) treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.