W.S. Song, C.S. Lee, K. Park, B. Suh, J.W. Kim, S. Kim, Y. Wee, S. Choi, H. Kang, S. Kim, K. Suh
{"title":"重新定义可靠性评估每一个新的内部通过铜泄漏退化","authors":"W.S. Song, C.S. Lee, K. Park, B. Suh, J.W. Kim, S. Kim, Y. Wee, S. Choi, H. Kang, S. Kim, K. Suh","doi":"10.1109/VLSIT.2002.1015462","DOIUrl":null,"url":null,"abstract":"By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Re-defining reliability assessment per new intra-via Cu leakage degradation\",\"authors\":\"W.S. Song, C.S. Lee, K. Park, B. Suh, J.W. Kim, S. Kim, Y. Wee, S. Choi, H. Kang, S. Kim, K. Suh\",\"doi\":\"10.1109/VLSIT.2002.1015462\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015462\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Re-defining reliability assessment per new intra-via Cu leakage degradation
By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.