先进的Cu/low-k (k=2.2)多级互连，用于0.10/0.07 /spl mu/m代

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015371

S. Jang, Y.H. Chen, T. Chou, S.N. Lee, C. Chen, T.C. Tseng, B.T. Chen, S.Y. Chang, C. Yu, M. Liang

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引用次数: 4

摘要

自旋介电介质(SOD, k=2.2)已与Cu集成0.10/0.07 /spl mu/m代。为了最小化互连电容，将传统的CVD帽层(k=4.5-7.5)替换为SOD介电介质(k=2.9)，并将多孔金属间介电介质(IMD)用作沟槽刻蚀的无停止层。无氮IMD工艺解决了光刻胶中毒问题。利用聚合物磨料和在低摩擦域设计的抛光参数进行平面化，首次实现了6级Cu/多孔SOD多层互连。电学测试结果表明，该结构具有良好的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0.07 /spl mu/m generation

A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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