{"title":"具有可扩展分辨率的75MS/s低功耗流水线ADC","authors":"D. Muthers, R. Tielert","doi":"10.1109/VDAT.2006.258135","DOIUrl":null,"url":null,"abstract":"A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 75MS/s Low Power Pipeline ADC with scalable Resolution\",\"authors\":\"D. Muthers, R. Tielert\",\"doi\":\"10.1109/VDAT.2006.258135\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258135\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 75MS/s Low Power Pipeline ADC with scalable Resolution
A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation
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