Test and characterization of a variable-capacity multilevel DRAM

Multilevel DRAM (MLDRAM) increases the storage density of DRAMs by using more than two data signal levels in the storage cells. An operational 19200-cell MLDRAM in 1.8-V 0.18-/spl mu/m mixed-signal CMOS is described that allows 1, 1.5, 2, 2.25 and 2.5 bits-per-cell operation using 2, 3, 4, 5 and 6 data signal levels, respectively. The MLDRAM uses reference and data cell signals that are generated in the cell array using charge sharing. The single-step sensing method uses multiple reference signals in parallel. Test chip characterization features include four cell sizes, two sense amplifier sizes, and bitline shields for half of the cells. New tests were developed based on an MLDRAM fault model. These include basic functionality, retention time, multilevel march, inter-bitline coupling, and cell-plate voltage bump tests. Our results show that the data and reference signals are generated correctly and that MLDRAM is possible for up to six signal levels.