铜/钨/铝复合互连临界应力及破坏机理的电迁移试验

Z.-S. Choi, Byung-lyul Park, Jong Myeong Lee, G. Choi, Hyeon-deok Lee, J. Moon
{"title":"铜/钨/铝复合互连临界应力及破坏机理的电迁移试验","authors":"Z.-S. Choi, Byung-lyul Park, Jong Myeong Lee, G. Choi, Hyeon-deok Lee, J. Moon","doi":"10.1109/IRPS.2009.5173360","DOIUrl":null,"url":null,"abstract":"Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect\",\"authors\":\"Z.-S. Choi, Byung-lyul Park, Jong Myeong Lee, G. Choi, Hyeon-deok Lee, J. Moon\",\"doi\":\"10.1109/IRPS.2009.5173360\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.\",\"PeriodicalId\":345860,\"journal\":{\"name\":\"2009 IEEE International Reliability Physics Symposium\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2009.5173360\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2009.5173360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文研究了下通孔铜金属化、上通孔铝金属化、中间通孔钨金属化的杂化互连中的电迁移问题。我们所测试的混合结构的铜段发生了致命的失效。在铜段中观察到两种不同的破坏机制。其中一种失效是由于钨孔阻挡金属与铜的界面上的空洞成核造成的。失效的时间高度依赖于所应用的障碍金属的类型。利用模拟工具获得了3种阻挡金属界面处空洞成核的临界应力,平均应力范围为61MPa ~ 246MPa。第二种类型的破坏比第一种类型发生的频率要低,是由空洞的生长和跨越线的宽度和厚度造成的。空洞生长的破坏发生在特定的时间范围内,并且破坏与障碍金属的变化无关,这表明破坏是由预先存在的空洞或缺陷引起的。因此,为了有效地提高这种混合互连结构的电磁电阻,不仅要优化屏障金属,还要尽量减少线路中存在的空洞或缺陷。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect
Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Life-stress relationship for thin film transistor gate line interconnects on flexible substrates The mechanism of device damage during bump process for flip-chip package Very fast transient simulation and measurement methodology for ESD technology development Field effect diode for effective CDM ESD protection in 45 nm SOI technology Reliability challenges for power devices under active cycling
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1