高可靠的PVD/ALD/PVD堆叠势垒金属结构，用于45纳米节点铜双damascene互连

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345664

K. Higashi, H. Yamaguchi, S. Omoto, A. Sakata, T. Katata, N. Matsunaga, H. Shibata

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引用次数: 8

摘要

在本文中，我们描述了用于45nm节点(140nm间距)高性能铜互连的高可靠屏障金属结构。研究了利用原子层沉积(ALD)工艺在低k ILD材料上利用TaN势垒金属存在的问题和解决方案，这是降低势垒金属厚度的关键技术。从影响可靠性的应力诱发空化(SiV)和电迁移(EM)耐久性等因素出发，提出了PVD/ALD/PVD堆叠势垒金属结构，实现了比传统工艺更低的布线电阻。我们区分了每一种PVD膜的作用，并提出了实现高可靠性铜双砷互连的最佳屏障金属结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects

In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.

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Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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