减少同步时序电路并发故障仿真中动态内存的使用

Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI:10.1109/ATS.1992.224433

K. Kim, K. Saluja

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引用次数: 2

摘要

提出并实现了一种将内存使用降至最低的策略。实现结果表明，所考虑的并发故障模拟器的动态内存使用确实低于其他常用的内存管理策略。实验结果表明，减小的内存占用大大提高了并发故障模拟器的性能。

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Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits

A strategy that reduces the memory usage to minimum is proposed and implemented. The results of implementation show that the dynamic memory usage of the concurrent fault simulator considered is indeed lower than other commonly used memory management strategies. It is shown through experimentation that the reduced memory usage improves substantially the performance of the concurrent fault simulator.<>

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Proceedings First Asian Test Symposium (ATS `92)

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