芯片级软误差电掩蔽建模与分析

S. Kiamehr, Mojtaba Ebrahimi, F. Firouzi, M. Tahoori
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引用次数: 18

摘要

随着超大规模集成电路技术的不断缩小,逻辑单元越来越容易受到辐射引起的软误差的影响。为了在芯片级准确地模拟这一点,应该准确地考虑电屏蔽的影响。此外,纳米级超大规模集成电路芯片复杂性的增加会导致芯片上的电压波动,从而影响电掩蔽。在本文中,我们提出了一种芯片级的电掩蔽分析,该分析准确地考虑了芯片上电压波动的影响。我们的分析表明,忽略电屏蔽中的电压波动会导致总体软误差率高达152%的不准确性。我们还提出了一种基于反向脉冲传播的技术来减少这种分析的运行时间。
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Chip-level modeling and analysis of electrical masking of soft errors
With continuous downscaling of VLSI technologies, logic cells are becoming more susceptible to radiation-induced soft error. To accurately model this at chip-level, the impact of electrical masking should be accurately considered. Moreover, increasing complexity of VLSI chips at nanoscale results in voltage fluctuation across the chip which impacts the electrical masking. In this paper, we present a chip-level electrical masking analysis which accurately considers the impact of voltage fluctuation across the chip. Our analysis shows that neglecting voltage fluctuation in electrical masking can lead up to 152% inaccuracy in the overall soft error rate. We also present a technique based on backward pulse propagation to reduce the runtime of this analysis.
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