{"title":"系统级设计的新策略","authors":"D. Gajski","doi":"10.1109/DDECS.2007.4295246","DOIUrl":null,"url":null,"abstract":"With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"169 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"New Strategies for System Level Design\",\"authors\":\"D. Gajski\",\"doi\":\"10.1109/DDECS.2007.4295246\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"169 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2007.4295246\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2007.4295246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure