{"title":"用于修复soc中多个ram的基础架构IP","authors":"Chao-Da Huang, Tsu-Wei Tseng, Jin-Fu Li","doi":"10.1109/VDAT.2006.258150","DOIUrl":null,"url":null,"abstract":"Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"An Infrastructure IP for Repairing Multiple RAMs in SOCs\",\"authors\":\"Chao-Da Huang, Tsu-Wei Tseng, Jin-Fu Li\",\"doi\":\"10.1109/VDAT.2006.258150\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258150\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Infrastructure IP for Repairing Multiple RAMs in SOCs
Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%
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