一种可制造的用于0.2 um以下DRAM技术的浅沟槽隔离工艺

半导体技术 Pub Date : 2002-08-07 DOI:10.1109/ASMC.2002.1001565

W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi

{"title":"一种可制造的用于0.2 um以下DRAM技术的浅沟槽隔离工艺","authors":"W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi","doi":"10.1109/ASMC.2002.1001565","DOIUrl":null,"url":null,"abstract":"A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies\",\"authors\":\"W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi\",\"doi\":\"10.1109/ASMC.2002.1001565\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.\",\"PeriodicalId\":64779,\"journal\":{\"name\":\"半导体技术\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"半导体技术\",\"FirstCategoryId\":\"1087\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2002.1001565\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"半导体技术","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ASMC.2002.1001565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

通过使用64M DRAM作为敏感监视器，演示了一种高度可制造且无缺陷的浅沟槽隔离(STI)工艺。在STI流程中，在拐角氧化(即衬里氧化)后进行特殊的额外退火(1100C)和在HDP CVD氧化沉积后进行RTA (1000C)退火，可以有效地减少硅应力相关的衬底缺陷，从而显著提高64M DRAM的良率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.

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半导体技术

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