圆片级3D集成电路的平面化良率限制

半导体技术 Pub Date : 2002-08-07 DOI:10.1109/ASMC.2002.1001618

M. Gupta, G. Rajagopalan, C. K. Hong, J. Lu, K. Rose, R. Gutmann

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引用次数: 3

摘要

将3D加工的平面化要求与传统2D加工的平面化要求进行比较，表明与2D集成电路所需的芯片平面度相比，晶圆级平面度对于3D来说是必不可少的。设计了一种屈服测试结构，用于研究在大马士革模压过程中发生的电气故障数量。该试验车辆的初步实验数据表明，平面度随着图案密度的变化而变化，尽管迄今尚未建立函数关系。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Planarization yield limiters for wafer-scale 3D ICs

The planarization requirements for 3D processing are compared to those for conventional 2D processing, indicating that wafer level planarity is essential for 3D as compared to the die level planarity needed for 2D ICs. A yield test structure has been designed to study the number of electrical faults that occur during damascene patterning. Initial experimental data with this test vehicle show that planarity changes with pattern density, although the functional relationship has not been established to date.

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半导体技术

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