{"title":"一种用于具有互补门源驱动的触发器的高速50%节能半摆时钟方案","authors":"Jin-Cheon Kim, Sanghoon Lee, Hong-June Park","doi":"10.1109/ICVC.1999.821004","DOIUrl":null,"url":null,"abstract":"A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"174 1","pages":"574-577"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive\",\"authors\":\"Jin-Cheon Kim, Sanghoon Lee, Hong-June Park\",\"doi\":\"10.1109/ICVC.1999.821004\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"174 1\",\"pages\":\"574-577\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.821004\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.821004","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive
A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.
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