Shiho Kim, Il-Suk Yang, Won-Jae Lee, I. You, B. Yu, K. Cho
{"title":"具有无损读出操作的单晶体管铁电RAM","authors":"Shiho Kim, Il-Suk Yang, Won-Jae Lee, I. You, B. Yu, K. Cho","doi":"10.1109/ICVC.1999.820955","DOIUrl":null,"url":null,"abstract":"A nonvolatile single transistor type FRAM is proposed. To overcome the selection problem of one-transistor-type FRAM, each well is isolated from adjacent columns, hence, the well bias can be controlled individually and can be floating state. The results of HSPICE simulations showed the successful operations of the proposed cell array. The worst gate disturb voltage of unselected cell is less than 2 V, which satisfies V/3 rule.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"218 1","pages":"433-436"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A single transistor ferroelectric RAM with nondestructive readout operations\",\"authors\":\"Shiho Kim, Il-Suk Yang, Won-Jae Lee, I. You, B. Yu, K. Cho\",\"doi\":\"10.1109/ICVC.1999.820955\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A nonvolatile single transistor type FRAM is proposed. To overcome the selection problem of one-transistor-type FRAM, each well is isolated from adjacent columns, hence, the well bias can be controlled individually and can be floating state. The results of HSPICE simulations showed the successful operations of the proposed cell array. The worst gate disturb voltage of unselected cell is less than 2 V, which satisfies V/3 rule.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"218 1\",\"pages\":\"433-436\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.820955\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single transistor ferroelectric RAM with nondestructive readout operations
A nonvolatile single transistor type FRAM is proposed. To overcome the selection problem of one-transistor-type FRAM, each well is isolated from adjacent columns, hence, the well bias can be controlled individually and can be floating state. The results of HSPICE simulations showed the successful operations of the proposed cell array. The worst gate disturb voltage of unselected cell is less than 2 V, which satisfies V/3 rule.