低k介电体的制造实施铜大马士革技术

H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien
{"title":"低k介电体的制造实施铜大马士革技术","authors":"H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien","doi":"10.1109/ASMC.2002.1001633","DOIUrl":null,"url":null,"abstract":"Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed \"Hammer\"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Manufacturing implementation of low-k dielectrics for copper damascene technology\",\"authors\":\"H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien\",\"doi\":\"10.1109/ASMC.2002.1001633\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed \\\"Hammer\\\"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.\",\"PeriodicalId\":64779,\"journal\":{\"name\":\"半导体技术\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"半导体技术\",\"FirstCategoryId\":\"1087\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2002.1001633\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"半导体技术","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ASMC.2002.1001633","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

先进的逻辑设备对后端集成提出了新的要求。新的高端处理器系列,如AMD Athlon/sup TM/和AMD的第八代处理器(代号为“Hammer”),需要引入低k铜层介电层(ILD)材料,以提高芯片速度并降低整体功耗。这对工具供应商和集成电路制造商来说都是一个具有挑战性的过程。半导体行业正在寻找一种低k解决方案,提供易于集成的高性能介电薄膜,同时具有高吞吐量和低拥有成本。基于关键技术和制造要求,Advanced Micro Devices公司选择了应用材料生产商系统用于低k介电工艺应用。在工艺流程中实施Black Diamond/sup TM/ (BD)和block /sup TM/,使集成k值<3.0,与氟化硅酸盐玻璃(F-TEOS)和氮化硅(SiN)相比,降低了20%。在Fab 30, AMD的先进的铜生产线,生产商已经证明了可靠和稳定的性能在传统介电薄膜沉积的大批量生产。本文的重点是将低k介电介质解决方案超越F-TEOS,以实现铜互连技术的完全制造就绪。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Manufacturing implementation of low-k dielectrics for copper damascene technology
Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed "Hammer"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
8436
期刊最新文献
A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies Ultra-dilute silicon wafer clean chemistry for fabrication of RF microwave devices Planarization yield limiters for wafer-scale 3D ICs Statistical modeling and analysis of wafer test fail counts An approach for improving yield with intentional defects
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1