Kihyun Choi, H. Sagong, Wonchang Kang, Hyunjin Kim, J. Hai, Miji Lee, Bomi Kim, Miji Lee, Soonyoung Lee, H. Shim, Junekyun Park, Youngwoo Cho, H. Rhee, S. Pae
{"title":"采用EUV技术的7nm制程技术可靠性增强","authors":"Kihyun Choi, H. Sagong, Wonchang Kang, Hyunjin Kim, J. Hai, Miji Lee, Bomi Kim, Miji Lee, Soonyoung Lee, H. Shim, Junekyun Park, Youngwoo Cho, H. Rhee, S. Pae","doi":"10.23919/VLSIT.2019.8776580","DOIUrl":null,"url":null,"abstract":"In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"13 1","pages":"T16-T17"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Enhanced Reliability of 7nm Process Technology featuring EUV\",\"authors\":\"Kihyun Choi, H. Sagong, Wonchang Kang, Hyunjin Kim, J. Hai, Miji Lee, Bomi Kim, Miji Lee, Soonyoung Lee, H. Shim, Junekyun Park, Youngwoo Cho, H. Rhee, S. Pae\",\"doi\":\"10.23919/VLSIT.2019.8776580\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"13 1\",\"pages\":\"T16-T17\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776580\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776580","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enhanced Reliability of 7nm Process Technology featuring EUV
In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.