在亚28nm节点上通过中间TSV集成的挑战

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI:10.1109/IITC.2014.6831869

H. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, Daniel Smith, Dingyou Zhang, Shan Gao

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引用次数: 6

摘要

这项工作提出了在亚28nm节点上使用一种新的涉及V0过孔的本地互连方案的通孔中间TSV集成。给出了各种V0方案，并给出了各自的电阻、电容和漏电流数据。通过TSV菊花链结构和MOL孔链给出了表征和可靠性结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Challenges to via middle TSV integration at sub-28nm nodes

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

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2021 IEEE International Interconnect Technology Conference (IITC)

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