三维NAND加工中晶圆翘曲的多尺度建模方法

O. O. Okudur, Mario Gonzalez, G. Van den bosch, M. Rosmeulen
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引用次数: 3

摘要

在不同的加工步骤中引入的机械应力,加上大的堆叠厚度,导致3-D NAND制造过程中的高晶圆翘曲。我们展示了一种局部(设备级)到全局(晶圆级)规模的有限元建模方法,该方法可用于评估具有缩放趋势的晶圆翘曲,并提供潜在的缓解策略。结果表明,局部应力的各向异性和翘曲的不对称性是在刻蚀狭缝后产生的,并在字线金属沉积过程中被放大。增加层数可以显著增加翘曲的幅度和不对称性。减少层厚度和使用低应力的金属,如钌和调整填料应力可以帮助减少与晶圆翘曲有关的问题。
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Multi-scale Modeling Approach to Assess and Mitigate Wafer Warpage in 3-D NAND Fabrication
Mechanical stresses introduced at various processing steps, combined with large stack thicknesses result in high wafer warpage during 3-D NAND fabrication. We demonstrate a local (device-level) to global (wafer-level) scale finite-element modeling approach that can be used to evaluate wafer warpage with scaling trends and offer potential mitigation strategies. It is shown that the anisotropy in local stresses and asymmetry in warpage are initiated after etching the slits and amplified by wordline metal deposition. Increasing number of layers is shown to significantly increase the magnitude and asymmetry of the warpage. Decreasing layer thicknesses and use of low-stress wordline metal such as Ruthenium and adjusting filler stresses can help reducing wafer-warpage related problems.
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