{"title":"通硅通孔材料性能变化对全芯片可靠性和时序的影响","authors":"Moongon Jung, D. Pan, S. Lim","doi":"10.1109/IITC.2014.6831846","DOIUrl":null,"url":null,"abstract":"We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"42 1","pages":"105-108"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Through-silicon-via material property variation impact on full-chip reliability and timing\",\"authors\":\"Moongon Jung, D. Pan, S. Lim\",\"doi\":\"10.1109/IITC.2014.6831846\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.\",\"PeriodicalId\":6823,\"journal\":{\"name\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"volume\":\"42 1\",\"pages\":\"105-108\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2014.6831846\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Through-silicon-via material property variation impact on full-chip reliability and timing
We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.