用于亚jtlnm LG的高性能应变锗栅极全环p沟道器件，具有优异的静电控制性能

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI:10.23919/VLSIT.2019.8776558

E. Capogreco, H. Arimura, L. Witters, A. Vohra, C. Porret, R. Loo, A. De Keersgieter, E. Dupuy, D. Marinov, A. Hikavyy, F. Sebaai, G. Mannaert, L. Ragnarsson, Y. Siew, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, E. Sanchez, F. Holstetns, S. Demuynck, K. Barla, V. De Heyn, D. Mocuta, N. Collaert, N. Horiguchi

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引用次数: 10

摘要

本文展示了高性能的张力p型双堆叠Ge gate - ali - around (GAA)器件，与我们之前的工作相比，栅极长度$(\text{L}_{\text{G}}\sim 25\text{nm})$显著减少。通过采用无扩展方案，在$\text{L}_{\text{G}}=25$ nm的范围内保持良好的静电控制，同时通过适当的间隔缩放和采用高b掺杂的Ge或GeSn作为源/漏极(S/D)材料来保持性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

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2019 Symposium on VLSI Technology

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