{"title":"下一代半导体制程成本分析的分层方法","authors":"R. Sandell, N. Pierce","doi":"10.1109/ASMC.2002.1001628","DOIUrl":null,"url":null,"abstract":"Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A hierarchical approach to cost analysis for next generation semiconductor processes\",\"authors\":\"R. Sandell, N. Pierce\",\"doi\":\"10.1109/ASMC.2002.1001628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.\",\"PeriodicalId\":64779,\"journal\":{\"name\":\"半导体技术\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"半导体技术\",\"FirstCategoryId\":\"1087\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2002.1001628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"半导体技术","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ASMC.2002.1001628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A hierarchical approach to cost analysis for next generation semiconductor processes
Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.
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