Kaizhen Han, Ying Wu, Y. Huang, Shengqiang Xu, Annie Kumar, E. Kong, Yuye Kang, Jishen Zhang, Chengkuan Wang, Haiwen Xu, Chen Sun, X. Gong
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引用次数: 6
摘要
通过形成200 mm晶圆尺寸的高质量GeSnOI衬底,首次将翅片宽度$(W_{fin})$为20 nm,翅片高度$(H_{{fin}})$为50 nm的互补finfet和互补隧道finfet (tffet)在同一衬底上共集成。GeSn n沟道和p沟道finfet以及tffet均实现了良好的电特性。我们还进行了仿真研究,以显示GeSnOI平台的前景,该平台不仅能够抑制关态泄漏电流,提高隧道fet的$ i {on}/ $ i {off}}比值,而且还可以提供强大的灵活性,使用反偏置来实现超越将Sn加入Ge的好处的优越电气特性。
First Demonstration of Complementary FinFETs and Tunneling FinFETs Co-Integrated on a 200 mm GeSnOI Substrate: A Pathway towards Future Hybrid Nano-electronics Systems
For the first time, complementary FinFETs and complementary tunneling FinFETs (TFFETs), with fin width $(W_{Fin})$ of 20 nm and fin height $(H_{{fin}})$ of 50 nm, were co-integrated on the same substrate, enabled by the formation of high-quality GeSn-on-insulator (GeSnOI) substrate with 200 mm wafer size. Decent electrical characteristics were realized for both GeSn n-and p-channel FinFETs and TFFETs. We also performed simulation studies to show the promise of the GeSnOI platform, which is not only able to suppress the off-state leakage current and improve the $I_{on}/I_{off}$ ratio of tunneling FETs, but can also provide the powerful flexibility of using a back bias to achieve superior electrical characteristics beyond the benefits of incorporating Sn into Ge.