Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology

High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents $(I_{\text{ds}})$ is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian $I_{\text{ds}}$ distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor $(R_{\text{ch}_{-}\text{f}})$ and source/drain external resistance $(R_{\text{ext}})$ is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.