Novel IR/EM-Aware Power Grid Design and Analysis Methodologies for Optimal PPA at Sub-10nm Technology Nodes

In this paper, we introduce novel, holistic, electromigration-(EM) and dynamic voltage drop-aware power grid (PG) design and analysis methods that can help resolve the critical limitations that guard-band-driven approaches of today’s modern design closure flows enforce upon physical designers in their quest to achieve the best possible power/performance/area (PPA). These methods can easily be integrated into any existing design flow. The proposed structured strategies to co-optimize inherent trade-offs in PG reliability and PPA improvement can help enable higher transistor density and accurately quantify the impact of IR drop for block-level timing within conventional automatic place-and-route (PnR) flows through the use of an exhaustive, but low-cost in-house solution. We demonstrate up to 9% area savings and up to 5% power reduction while maintaining achievable frequency. The proposed flow updates pave the path for future work to apply our machine-learning-enhanced design space exploration approaches to better control trade-offs between PG reliability and PPA improvement.