A cell selection algorithm for area minimization

This paper presents a cell selection algorithm that minimizes the area of the cell-based design, while satisfying the given delay constraint. The proposed algorithm visits the given circuit in the forward direction and calculates the lower bound on the delay and area. Then, it visits the circuit in the reverse direction, and binds the logic gates with library cells using the Branch-and-Bound formulations of the lower bound. Experimental results show that the proposed algorithm minimizes the area of test circuits by 27.33% on the average.