Self-timed shared division and square-root implementation using full redundant signed digit numbers

A radix-2 square root implementation for self-timed dividers using redundant signed-digit (RSD) adders is presented. In this method, two self-timed RSD adder stages are used for each result bit selection. A very efficient and simple result bit selection logic compared to the previous designs is implemented by using double self-timed ring stages. The F-term in the RSD format is easily applied to two self-time substages. F-term generation is overlapped with a partial remainder calculation and result-bit selection. This makes the hardware implementation of the F-term generation much easier and less time-constraint. No additional time delay is included in the square-root arithmetic. From the SPICE simulation at 35/spl deg/C and under MOSIS 1.2 /spl mu/m design rule, the speed of this design is estimated to be 124 ns for 54 bit square-root and division calculation.