{"title":"一个4- 400mhz抖动抑制延迟锁定环分频方法","authors":"Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim","doi":"10.1109/ICVC.1999.820925","DOIUrl":null,"url":null,"abstract":"This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"60 1","pages":"339-341"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method\",\"authors\":\"Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim\",\"doi\":\"10.1109/ICVC.1999.820925\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"60 1\",\"pages\":\"339-341\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.820925\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820925","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method
This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.
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