A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems

R. Fischbach, T. Horst, J. Lienig
{"title":"A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems","authors":"R. Fischbach, T. Horst, J. Lienig","doi":"10.1109/3DIC48104.2019.9058886","DOIUrl":null,"url":null,"abstract":"Micro-transfer printing (μTP) is a promising assembly technology that enables heterogeneous integration of dies originating from different wafers. It combines the advantages of pick-and-place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. μTP applies an elastomer stamp to transfer multiple dies from source to target wafers in parallel. Increasing the stamp size allows for the transfer of more dies at once and reciprocally shortens the manufacturing time, enabling extensive cost reductions. On the other hand, larger stamps result in a lower wafer utilization, thereby causing increases in costs. Finding the cost-optimal stamp layout is one of the key tasks when designing heterogeneous systems for μTP. There is no trivial solution to calculate the wafer utilization needed to evaluate the quality of a stamp layout. Based on a graph problem known as maximum independent set, we propose a model to determine the wafer utilization subject to the stamp and wafer layout. We demonstrate the application of our model within an economic cost function to optimize a μTP design with regard to manufacturing costs.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC48104.2019.9058886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Micro-transfer printing (μTP) is a promising assembly technology that enables heterogeneous integration of dies originating from different wafers. It combines the advantages of pick-and-place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. μTP applies an elastomer stamp to transfer multiple dies from source to target wafers in parallel. Increasing the stamp size allows for the transfer of more dies at once and reciprocally shortens the manufacturing time, enabling extensive cost reductions. On the other hand, larger stamps result in a lower wafer utilization, thereby causing increases in costs. Finding the cost-optimal stamp layout is one of the key tasks when designing heterogeneous systems for μTP. There is no trivial solution to calculate the wafer utilization needed to evaluate the quality of a stamp layout. Based on a graph problem known as maximum independent set, we propose a model to determine the wafer utilization subject to the stamp and wafer layout. We demonstrate the application of our model within an economic cost function to optimize a μTP design with regard to manufacturing costs.
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基于图的成本优化异构2.5D系统微转移打印模型
微转移印刷(μTP)是一种很有前途的组装技术,可以实现来自不同晶圆的模具的异质集成。它结合了在灵活性方面的取放优势和在高吞吐量方面的晶圆级加工优势。μTP采用弹性体印记将多个晶片从源晶片并行转移到目标晶片。增加印章尺寸允许转移更多的模具一次,并相应地缩短制造时间,使广泛的成本降低。另一方面,更大的印章会导致晶圆利用率降低,从而导致成本增加。寻找成本最优的印章布局是设计μTP异构系统的关键任务之一。没有简单的解决方案来计算评估邮票布局质量所需的晶圆利用率。基于最大独立集的图问题,我们提出了一个模型来确定晶圆利用率受邮票和晶圆布局的影响。我们演示了我们的模型在经济成本函数中的应用,以优化μTP设计的制造成本。
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