Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058778
K. Takemura, A. Ukita, Y. Ibusuki, M. Kurihara, A. Noriki, T. Amano, D. Okamoto, Yasuyuki Suzuki, K. Kurata
Three-dimensional optical and electrical I/O structures for chip-scale Si photonic optical transceivers have been developed. The optical I/O structure, which is called an “optical pin,” has a vertical polymer waveguide structure. The waveguide structure has 125- $mu$ m-pitch 8°-tilted cores. The tilted cores were formed by oblique-illuminated exposure. The electrical I/O structure comprises 250- $mu$ m-pitch regularly-arranged through-glass-vias. As these I/O structures are configured on the same side of the Si photonic module, the configuration enables simultaneous optical and electrical bonding to a polymer-waveguide-embedded printed circuit board. The developed I/O structures minimize the packaging area and support 25-Gbps multimode transmission.
{"title":"Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic Transceivers","authors":"K. Takemura, A. Ukita, Y. Ibusuki, M. Kurihara, A. Noriki, T. Amano, D. Okamoto, Yasuyuki Suzuki, K. Kurata","doi":"10.1109/3DIC48104.2019.9058778","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058778","url":null,"abstract":"Three-dimensional optical and electrical I/O structures for chip-scale Si photonic optical transceivers have been developed. The optical I/O structure, which is called an “optical pin,” has a vertical polymer waveguide structure. The waveguide structure has 125- $mu$ m-pitch 8°-tilted cores. The tilted cores were formed by oblique-illuminated exposure. The electrical I/O structure comprises 250- $mu$ m-pitch regularly-arranged through-glass-vias. As these I/O structures are configured on the same side of the Si photonic module, the configuration enables simultaneous optical and electrical bonding to a polymer-waveguide-embedded printed circuit board. The developed I/O structures minimize the packaging area and support 25-Gbps multimode transmission.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115660080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058881
K. Hachiya, A. Kurokawa
A novel method is proposed to improve diagnostic performance and to decrease probability of false diagnoses in testing open defects of TSVs (Through Silicon Vias) in PDN (Power Distribution Network) of 3D-ICs (Three Dimensional Integrated Circuits). The conventional method measures resistances between microbumps placed exactly under TSVs and detects defects of the TSVs by changes of the resistances. But it suffers from manufacturing variabilities which also cause changes of the resistances even without any defect, and its diagnostic performance is not enough for practical applications. In this paper, a method is proposed which measures resistance of another microbump pair to cancel the variabilities in addition to each resistance for detecting an open defect, and improves its diagnostic performance by cancelling the variabilities in the detecting resistance. Experimental simulations are conducted using a 3D-IC example with two dies. The results show that the diagnostic performances by the conventional method are improved by the proposed variability cancellation and reach the practical level.
{"title":"Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC","authors":"K. Hachiya, A. Kurokawa","doi":"10.1109/3DIC48104.2019.9058881","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058881","url":null,"abstract":"A novel method is proposed to improve diagnostic performance and to decrease probability of false diagnoses in testing open defects of TSVs (Through Silicon Vias) in PDN (Power Distribution Network) of 3D-ICs (Three Dimensional Integrated Circuits). The conventional method measures resistances between microbumps placed exactly under TSVs and detects defects of the TSVs by changes of the resistances. But it suffers from manufacturing variabilities which also cause changes of the resistances even without any defect, and its diagnostic performance is not enough for practical applications. In this paper, a method is proposed which measures resistance of another microbump pair to cancel the variabilities in addition to each resistance for detecting an open defect, and improves its diagnostic performance by cancelling the variabilities in the detecting resistance. Experimental simulations are conducted using a 3D-IC example with two dies. The results show that the diagnostic performances by the conventional method are improved by the proposed variability cancellation and reach the practical level.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058901
G. Sisto, P. Debacker, Rongmei Chen, G. V. D. Plas, R. Chou, E. Beyne, D. Milojevic
We present extensions to commercially available EDA tools to support Wafer-to-Wafer (W2W), Face-to-Face (F2F), hybrid bonding 3D integration with ~1μm pitch Cupad structures. Proposed flow is based on Innovus™ Place & Route (P&R) tool from Cadence Design Systems and allows functional 3D system partitioning with user specified partitioning information and automated netlist split. Due to fine 3D pitch, the partitioning can occur at lower levels of system hierarchy, resulting in significant number of 3D pins and with die-crossing critical paths. Proposed flow has been validated using memory-on-logic split of a single OpenSPARC-T2 core. L1 memory macros have been extracted from the post-synthesized gate-level netlist using a dedicated automated netlist partitioner. Per die netlists and top-level system have been fed into the P&R flow, memory die being implemented first. 3D structures have been assigned to 3D nets automatically, allowing their optimal placement with respect to the memory macros pins. 3D pin positions of the memory die have been propagated as a constraint for the implementation of the logic die, allowing optimized standard cell placement with respect to the 3D pins. Finally, we have enabled a cross-die timing analysis to assess the improvements of 3D in comparison to 2D. Our results show up to 40% of the total wirelength savings and 25 % on the maximum one, resulting in a 19% timing improvement on critical path.
{"title":"Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route","authors":"G. Sisto, P. Debacker, Rongmei Chen, G. V. D. Plas, R. Chou, E. Beyne, D. Milojevic","doi":"10.1109/3DIC48104.2019.9058901","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058901","url":null,"abstract":"We present extensions to commercially available EDA tools to support Wafer-to-Wafer (W2W), Face-to-Face (F2F), hybrid bonding 3D integration with ~1μm pitch Cupad structures. Proposed flow is based on Innovus™ Place & Route (P&R) tool from Cadence Design Systems and allows functional 3D system partitioning with user specified partitioning information and automated netlist split. Due to fine 3D pitch, the partitioning can occur at lower levels of system hierarchy, resulting in significant number of 3D pins and with die-crossing critical paths. Proposed flow has been validated using memory-on-logic split of a single OpenSPARC-T2 core. L1 memory macros have been extracted from the post-synthesized gate-level netlist using a dedicated automated netlist partitioner. Per die netlists and top-level system have been fed into the P&R flow, memory die being implemented first. 3D structures have been assigned to 3D nets automatically, allowing their optimal placement with respect to the memory macros pins. 3D pin positions of the memory die have been propagated as a constraint for the implementation of the logic die, allowing optimized standard cell placement with respect to the 3D pins. Finally, we have enabled a cross-die timing analysis to assess the improvements of 3D in comparison to 2D. Our results show up to 40% of the total wirelength savings and 25 % on the maximum one, resulting in a 19% timing improvement on critical path.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126800680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058785
M. Goto, J. D. Vos, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, E. Higurashi, Y. Honda, T. Saraya, M. Kobayashi, H. Toshiyoshi, T. Hiramoto
We report a triple-layering technology for pixelparallel CMOS image sensors. Photodiodes (PDs), logic circuits, and 16-bit pulse counters are developed on silicon-on-insulator (SOI) wafers, and they are three-dimensionally integrated within every pixel by using hybrid bonding through damascened Au electrodes of 5 pm in diameter in a SiO2 insulator. The developed triple-stacked wafers are confirmed to have no voids or separation of layers even after the removal of the handle layer, thereby demonstrating the feasibility of multi-layered imaging devices for the next-generation video systems.
{"title":"Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers","authors":"M. Goto, J. D. Vos, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, E. Higurashi, Y. Honda, T. Saraya, M. Kobayashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/3DIC48104.2019.9058785","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058785","url":null,"abstract":"We report a triple-layering technology for pixelparallel CMOS image sensors. Photodiodes (PDs), logic circuits, and 16-bit pulse counters are developed on silicon-on-insulator (SOI) wafers, and they are three-dimensionally integrated within every pixel by using hybrid bonding through damascened Au electrodes of 5 pm in diameter in a SiO2 insulator. The developed triple-stacked wafers are confirmed to have no voids or separation of layers even after the removal of the handle layer, thereby demonstrating the feasibility of multi-layered imaging devices for the next-generation video systems.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123937089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058870
F. Inoue, J. Bertheau, S. Suhard, A. Phommahaxay, T. Ohashi, T. Kinoshita, Y. Kinoshita, E. Beyne
Blade dicing compatible particle protective layer is investigated for feasibility study of collective Die-to- Wafer (D2W) direct bonding. Having the compatibility to blade dicing, the protective layer needs to be insoluble for de-ionized water (DIW), because blade dicing requires cooling water to maintain the cutting performance. Therefore, polymers soluble in alkaline solutions (e.g. TMAH, NH4OH), however, insoluble in DIW are tested for collective die to wafer direct bonding. With the dicing particle protective layer technology, successful collective die to wafer direct bonding with current die assembly tools are achieved. The alternative protective layer ensures high yield and cost of ownership for collective die to wafer integration
{"title":"Protective Layer for Collective Die to Wafer Hybrid Bonding","authors":"F. Inoue, J. Bertheau, S. Suhard, A. Phommahaxay, T. Ohashi, T. Kinoshita, Y. Kinoshita, E. Beyne","doi":"10.1109/3DIC48104.2019.9058870","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058870","url":null,"abstract":"Blade dicing compatible particle protective layer is investigated for feasibility study of collective Die-to- Wafer (D2W) direct bonding. Having the compatibility to blade dicing, the protective layer needs to be insoluble for de-ionized water (DIW), because blade dicing requires cooling water to maintain the cutting performance. Therefore, polymers soluble in alkaline solutions (e.g. TMAH, NH4OH), however, insoluble in DIW are tested for collective die to wafer direct bonding. With the dicing particle protective layer technology, successful collective die to wafer direct bonding with current die assembly tools are achieved. The alternative protective layer ensures high yield and cost of ownership for collective die to wafer integration","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058839
K. Sumita, J. Takeyasu, Kimihiko Kato, K. Toprasertpong, M. Takenaka, S. Takagi
InAs-On-Insulator structures are fabricated by the Smart Cut process and reusability of the donor InAs wafer without the degradation of film quality is also demonstrated. The effects of thermal annealing, which is expected to recover the damage induced by the implantation process, on the InAs-OI quality are studied. It is shown that annealing at 500 °C is effective to recover the crystallinity in terms of the Raman spectra and the electron mobility. No difference between InAs-OI fabricated with the original InAs wafer and the reused InAs wafer is observed. As a result, 140-nm-thick (111) InAs-OI fabricated by the reusing process is shown to have the electron Hall mobility of 6500 cm2/Vs and the carrier density of 6 × 1017 cm−3.
{"title":"Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs Wafers","authors":"K. Sumita, J. Takeyasu, Kimihiko Kato, K. Toprasertpong, M. Takenaka, S. Takagi","doi":"10.1109/3DIC48104.2019.9058839","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058839","url":null,"abstract":"InAs-On-Insulator structures are fabricated by the Smart Cut process and reusability of the donor InAs wafer without the degradation of film quality is also demonstrated. The effects of thermal annealing, which is expected to recover the damage induced by the implantation process, on the InAs-OI quality are studied. It is shown that annealing at 500 °C is effective to recover the crystallinity in terms of the Raman spectra and the electron mobility. No difference between InAs-OI fabricated with the original InAs wafer and the reused InAs wafer is observed. As a result, 140-nm-thick (111) InAs-OI fabricated by the reusing process is shown to have the electron Hall mobility of 6500 cm2/Vs and the carrier density of 6 × 1017 cm−3.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133122855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058871
P. Ramm, A. Klumpp, C. Landesberger, J. Weber, A. Heinig, P. Schneider, Guenter Elst, M. Engelhardt
Pioneering contributions of Fraunhofer in the field of 3D IC integration are presented, as well as recent 3D design and technology developments with a dedicated focus on the application of heterogeneous systems.
{"title":"Fraunhofer's Initial and Ongoing Contributions in 3D IC Integration","authors":"P. Ramm, A. Klumpp, C. Landesberger, J. Weber, A. Heinig, P. Schneider, Guenter Elst, M. Engelhardt","doi":"10.1109/3DIC48104.2019.9058871","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058871","url":null,"abstract":"Pioneering contributions of Fraunhofer in the field of 3D IC integration are presented, as well as recent 3D design and technology developments with a dedicated focus on the application of heterogeneous systems.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114463742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058862
Y. Araga, K. Kikuchi, M. Aoyagi
Multi chip modules (MCMs) employing three-dimensionally stacked ICs (3DS-ICs) are expected to be the integration method to achieve high performance by integrating memories and processors densely. In such a densely assembled modules, crosstalk between closely placed 3DS-ICs like a stacked memories and processors. In this study, we propose a shielding method using through-silicon vias (TSVs) to suppress stack-to-stack crosstalk, we created MCM model for 3-D electromagnetic solver and simulated result showed good noise suppression effect, simulation result also showed higher suppression ratio as larger number of stacked ICs.
{"title":"Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs","authors":"Y. Araga, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC48104.2019.9058862","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058862","url":null,"abstract":"Multi chip modules (MCMs) employing three-dimensionally stacked ICs (3DS-ICs) are expected to be the integration method to achieve high performance by integrating memories and processors densely. In such a densely assembled modules, crosstalk between closely placed 3DS-ICs like a stacked memories and processors. In this study, we propose a shielding method using through-silicon vias (TSVs) to suppress stack-to-stack crosstalk, we created MCM model for 3-D electromagnetic solver and simulated result showed good noise suppression effect, simulation result also showed higher suppression ratio as larger number of stacked ICs.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114560173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058864
I. Jani, D. Lattard, P. Vivet, L. Arnaud, E. Beigné
3D integration is a promising solution to meet the increased need for functionality, density and performance of future integrated circuits. It is an attractive technique to address the requirements of several applications such as smart imagers, high-performance computing and memory-on-logic folding. However, test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this paper, the causes of local misalignment are well detailed. Then, a simulation using Matlab tool is illustrated and finally the impact of misalignment defect on resistance and capacitance parameters is demonstrated.
{"title":"Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects","authors":"I. Jani, D. Lattard, P. Vivet, L. Arnaud, E. Beigné","doi":"10.1109/3DIC48104.2019.9058864","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058864","url":null,"abstract":"3D integration is a promising solution to meet the increased need for functionality, density and performance of future integrated circuits. It is an attractive technique to address the requirements of several applications such as smart imagers, high-performance computing and memory-on-logic folding. However, test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this paper, the causes of local misalignment are well detailed. Then, a simulation using Matlab tool is illustrated and finally the impact of misalignment defect on resistance and capacitance parameters is demonstrated.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122100606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There is a serious problem of poor sidewall coverage for the sputtered barrier metals in high aspect ratio TSVs, and it is becoming difficult for complete filling of Cu. We have proposed electroless plated Co-alloy barrier metals for replacing conventional sputtered barrier metals. In this study, we evaluated Cu diffusion barrier properties of various electroless CoWB films with different atomic compositions. CoWB and CoB films were electroless plated on Pd nanoparticle catalyst. A typical structure for evaluation of interdiffusion is stacked layers of TiN/Cu/CoWB barrier layer/thin SiCh/Si substrate. We evaluated Cu interdiffusion characteristics after annealing by SIMS depth profiling. The ratio of the atomic composition of CoWB were varied by tuning plating bath conditions. It was shown that an electroless CoWB film with W content larger than 15% had a good Cu diffusion barrier property against 350 °C annealing.
{"title":"Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO2/Si Substrate for Via-last TSV Application","authors":"Taro Matsudaira, Shunsuke Shindo, Tomohiro Shimizu, T. Ito, Shoso Shinguhara, Satoru Shimizu","doi":"10.1109/3DIC48104.2019.9058791","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058791","url":null,"abstract":"There is a serious problem of poor sidewall coverage for the sputtered barrier metals in high aspect ratio TSVs, and it is becoming difficult for complete filling of Cu. We have proposed electroless plated Co-alloy barrier metals for replacing conventional sputtered barrier metals. In this study, we evaluated Cu diffusion barrier properties of various electroless CoWB films with different atomic compositions. CoWB and CoB films were electroless plated on Pd nanoparticle catalyst. A typical structure for evaluation of interdiffusion is stacked layers of TiN/Cu/CoWB barrier layer/thin SiCh/Si substrate. We evaluated Cu interdiffusion characteristics after annealing by SIMS depth profiling. The ratio of the atomic composition of CoWB were varied by tuning plating bath conditions. It was shown that an electroless CoWB film with W content larger than 15% had a good Cu diffusion barrier property against 350 °C annealing.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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