{"title":"Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI","authors":"M. Murugesan, M. Koyanagi, T. Fukushima","doi":"10.1109/3DIC48104.2019.9058853","DOIUrl":null,"url":null,"abstract":"A feasibility study for the continuous formation of multi-layer graphene (MLG) on both through-Si-via (TSV) top surface and all through the TSV sidewall and the bottom surface of high-aspect-ratio TSV by thermal chemical vapor deposition (CVD) technique has been carried out. Both microstructural and μ-Raman studies on cross-sectional graphene-TSV samples confirmed that the continuous formation of MLG all along the TSV side wall for the CVD growth temperatures of 650°C and above, and it may be used as thermal TSVs for heat removal in the stacked tiers of 3D-LSI/IC.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC48104.2019.9058853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A feasibility study for the continuous formation of multi-layer graphene (MLG) on both through-Si-via (TSV) top surface and all through the TSV sidewall and the bottom surface of high-aspect-ratio TSV by thermal chemical vapor deposition (CVD) technique has been carried out. Both microstructural and μ-Raman studies on cross-sectional graphene-TSV samples confirmed that the continuous formation of MLG all along the TSV side wall for the CVD growth temperatures of 650°C and above, and it may be used as thermal TSVs for heat removal in the stacked tiers of 3D-LSI/IC.
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