Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs

Abstract

A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce impedance of power delivery networks (PDNs). A thick Cu backside buried metal (BBM) in Si Interposer provides low resistive power/ground wiring and also forms a large parasitic bypass capacitance between power and ground patterns, which drastically suppresses the power supply noise. The Si interposer was implemented over an cryptographic chip with a large scale digital circuit fabricated in 130 nm CMOS. An internal noise monitoring circuit embedded in the CMOS chip indicates it that the proposed over-the-top Si interposer (OVTT-SiIP) reduces a peak-to-peak power supply noise and DC drop during cryptographic operation to less than 50%.