{"title":"Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs","authors":"V.N. Rayapati, B. Kaminska","doi":"10.1109/MT.1993.263137","DOIUrl":null,"url":null,"abstract":"In this paper two dynamic reconfiguration schemes are discussed for mega bit BiCMOS SRAMs. These schemes allow the failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved respectively, as compared to the conventional methods.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"142 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1993 IEEE International Workshop on Memory Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MT.1993.263137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper two dynamic reconfiguration schemes are discussed for mega bit BiCMOS SRAMs. These schemes allow the failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved respectively, as compared to the conventional methods.<>
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