The author presents an effective method of testing spot defects causing delay faults in SRAM circuits, without having to perform a full speed test of every single cell in a chip. The method is based on the detection of spot defects through the imbalance they cause to memory cells by transforming the imbalance effect into a permanent error. Such tests may be performed at a low speed, while retaining an excellent ability to detect non-catastrophic spot defects.<>
{"title":"An inexpensive method of detecting localised parametric defects in static RAM","authors":"Y. Savaria, C. Thibeault","doi":"10.1109/MT.1993.263143","DOIUrl":"https://doi.org/10.1109/MT.1993.263143","url":null,"abstract":"The author presents an effective method of testing spot defects causing delay faults in SRAM circuits, without having to perform a full speed test of every single cell in a chip. The method is based on the detection of spot defects through the imbalance they cause to memory cells by transforming the imbalance effect into a permanent error. Such tests may be performed at a low speed, while retaining an excellent ability to detect non-catastrophic spot defects.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"927 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124569797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Khare, S. Griep, H.-D. Oberle, W. Maly, D. Schmitt-Landsiedel, U. Kollmer, D. Walker
Yield learning-a key process in assuring manufacturing efficiency-must be based on effective defect diagnostic procedures. One such procedure, using measurements of SRAMs and a computer-generated defect-fault dictionary, is presented in this paper. The discussion is focused on the 'resolution of diagnosis', which is the ability to resolve as large a variety of defects as possible. To assess the resolution limits, an experiment involving dictionary generation and SRAM testing was conducted. The test results were compared against simulated bitmaps, and the differences were analyzed using failure analysis. The results obtained confirmed that defect simulation-based diagnosis can be very effective. It can also be enhanced if appropriate SRAM designs, testing strategies and defect models are chosen.<>
{"title":"Key attributes of an SRAM testing strategy required for effective process monitoring","authors":"J. Khare, S. Griep, H.-D. Oberle, W. Maly, D. Schmitt-Landsiedel, U. Kollmer, D. Walker","doi":"10.1109/MT.1993.263144","DOIUrl":"https://doi.org/10.1109/MT.1993.263144","url":null,"abstract":"Yield learning-a key process in assuring manufacturing efficiency-must be based on effective defect diagnostic procedures. One such procedure, using measurements of SRAMs and a computer-generated defect-fault dictionary, is presented in this paper. The discussion is focused on the 'resolution of diagnosis', which is the ability to resolve as large a variety of defects as possible. To assess the resolution limits, an experiment involving dictionary generation and SRAM testing was conducted. The test results were compared against simulated bitmaps, and the differences were analyzed using failure analysis. The results obtained confirmed that defect simulation-based diagnosis can be very effective. It can also be enhanced if appropriate SRAM designs, testing strategies and defect models are chosen.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130733138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.<>
{"title":"On-line and off-line testable design of random access memories","authors":"S. Subramanian, P. Lala","doi":"10.1109/MT.1993.263154","DOIUrl":"https://doi.org/10.1109/MT.1993.263154","url":null,"abstract":"The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133121161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper two dynamic reconfiguration schemes are discussed for mega bit BiCMOS SRAMs. These schemes allow the failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved respectively, as compared to the conventional methods.<>
{"title":"Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs","authors":"V.N. Rayapati, B. Kaminska","doi":"10.1109/MT.1993.263137","DOIUrl":"https://doi.org/10.1109/MT.1993.263137","url":null,"abstract":"In this paper two dynamic reconfiguration schemes are discussed for mega bit BiCMOS SRAMs. These schemes allow the failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved respectively, as compared to the conventional methods.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116590387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author presents part qualification, characterization and testing procedures for memory (static/dynamic RAM) components, intended for military and aerospace use. The procedures provide quick and low cost evaluation of commercial technology transferred to mil/aerospace systems.<>
{"title":"Radiation and life test procedures for military and aerospace memory components","authors":"R. Chrusciel","doi":"10.1109/MT.1993.263139","DOIUrl":"https://doi.org/10.1109/MT.1993.263139","url":null,"abstract":"The author presents part qualification, characterization and testing procedures for memory (static/dynamic RAM) components, intended for military and aerospace use. The procedures provide quick and low cost evaluation of commercial technology transferred to mil/aerospace systems.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors' research has led to: (1) the development of original rules for the conversion of single-bit march tests into multi-bit march tests; (2) the transformation of the new multi-bit march tests, using a 'serial shifting notation' which represents 'serial access' in embedded RAMs, into serial-access word-oriented march tests; and (3) the introduction of a new compact notation which extends the well-established march notation to include algorithms with two levels of FOR-loops (namely: the Galloping FOR-loop and the Hamming FOR-loop), since such algorithms are indispensible for locating coupling faults in cell arrays, and stuck-open faults in address decoders. Finally, a tabular summary (using both the 'hybrid serial/parallel' and the 'modular' data accessing modes) of fault location algorithms is given.<>
{"title":"Fault location algorithms for repairable embedded RAMs","authors":"R. Treuer, V. Agarwal","doi":"10.1109/MT.1993.263149","DOIUrl":"https://doi.org/10.1109/MT.1993.263149","url":null,"abstract":"The authors' research has led to: (1) the development of original rules for the conversion of single-bit march tests into multi-bit march tests; (2) the transformation of the new multi-bit march tests, using a 'serial shifting notation' which represents 'serial access' in embedded RAMs, into serial-access word-oriented march tests; and (3) the introduction of a new compact notation which extends the well-established march notation to include algorithms with two levels of FOR-loops (namely: the Galloping FOR-loop and the Hamming FOR-loop), since such algorithms are indispensible for locating coupling faults in cell arrays, and stuck-open faults in address decoders. Finally, a tabular summary (using both the 'hybrid serial/parallel' and the 'modular' data accessing modes) of fault location algorithms is given.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132078031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behavior of two different ECL storage element implementations are examined in the presence of physical faults. While fault models for some implementations of CMOS storage elements have been examined, not much attention has been paid to ECL storage elements. The conventional stuck-at fault model termed minimal fault model assumes that an input (output) of a storage element can be stuck-at-1 or 0. The minimal fault model may not model the behavior under certain physical failures in a storage element. The enhanced fault model providing higher coverage of physical failures is presented.<>
{"title":"Modeling of faulty behavior of ECL storage elements","authors":"S. Menon, Y. Malaiya, A. Jayasumana","doi":"10.1109/MT.1993.263153","DOIUrl":"https://doi.org/10.1109/MT.1993.263153","url":null,"abstract":"Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behavior of two different ECL storage element implementations are examined in the presence of physical faults. While fault models for some implementations of CMOS storage elements have been examined, not much attention has been paid to ECL storage elements. The conventional stuck-at fault model termed minimal fault model assumes that an input (output) of a storage element can be stuck-at-1 or 0. The minimal fault model may not model the behavior under certain physical failures in a storage element. The enhanced fault model providing higher coverage of physical failures is presented.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114763045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the authors present a new class of fault models called duplex pattern sensitive faults that represents more accurately the actual faults that can occur in dual-port DRAMs. Then, they propose an efficient linear test algorithm that allows 100% fault coverage for the considered fault model.<>
{"title":"A new class of fault models and test algorithms for dual-port dynamic RAM testing","authors":"V. Castro Alves, O. Kebichi, Á. Ferreira","doi":"10.1109/MT.1993.263147","DOIUrl":"https://doi.org/10.1109/MT.1993.263147","url":null,"abstract":"In this paper, the authors present a new class of fault models called duplex pattern sensitive faults that represents more accurately the actual faults that can occur in dual-port DRAMs. Then, they propose an efficient linear test algorithm that allows 100% fault coverage for the considered fault model.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134255002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented.<>
{"title":"Effective tests for memories based on faults models for low PPM defects","authors":"D. Lam, S. Y. Khim","doi":"10.1109/MT.1993.263142","DOIUrl":"https://doi.org/10.1109/MT.1993.263142","url":null,"abstract":"The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121694507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RAM testing has become a crucial problem because the testing time becomes much longer with the increase of its capacity. In this paper, the authors propose a current testing for CMOS static RAMs. Firstly, to see what influence a fault has on a power supply current, they analyze the behavior of a single memory cell when a fault occurs. It is found that almost all faults affect power supply current when a write operation is executed. Based on this analysis, secondly, the authors discuss a current testing scheme, where an address decoder structure is modified such that a write operation can be simultaneously executed on all the memory cells in a testing mode. In this current testing scheme, since the whole memory cell array could be treated as if it were a single memory cell, the length of the test sequences is not dependent on the size of memory cell array and must be very short. Hence, the authors believe their current testing method is a promising candidate for testing CMOS static RAMs.<>
{"title":"A current testing for CMOS static RAMs","authors":"H. Yokoyama, H. Tamamoto, Y. Narita","doi":"10.1109/MT.1993.263135","DOIUrl":"https://doi.org/10.1109/MT.1993.263135","url":null,"abstract":"RAM testing has become a crucial problem because the testing time becomes much longer with the increase of its capacity. In this paper, the authors propose a current testing for CMOS static RAMs. Firstly, to see what influence a fault has on a power supply current, they analyze the behavior of a single memory cell when a fault occurs. It is found that almost all faults affect power supply current when a write operation is executed. Based on this analysis, secondly, the authors discuss a current testing scheme, where an address decoder structure is modified such that a write operation can be simultaneously executed on all the memory cells in a testing mode. In this current testing scheme, since the whole memory cell array could be treated as if it were a single memory cell, the length of the test sequences is not dependent on the size of memory cell array and must be very short. Hence, the authors believe their current testing method is a promising candidate for testing CMOS static RAMs.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126000467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：