Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects

I. Jani, D. Lattard, P. Vivet, L. Arnaud, E. Beigné
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引用次数: 2

Abstract

3D integration is a promising solution to meet the increased need for functionality, density and performance of future integrated circuits. It is an attractive technique to address the requirements of several applications such as smart imagers, high-performance computing and memory-on-logic folding. However, test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this paper, the causes of local misalignment are well detailed. Then, a simulation using Matlab tool is illustrated and finally the impact of misalignment defect on resistance and capacitance parameters is demonstrated.
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高密度3D-IC互连的不对准分析及电学性能
3D集成是一种很有前途的解决方案,可以满足未来集成电路对功能、密度和性能日益增长的需求。它是一种有吸引力的技术,可以满足智能成像仪、高性能计算和存储逻辑折叠等应用的需求。然而,这种细粒度3D互连的测试和表征仍然是一个悬而未决的问题;由于制造工艺的原因,Cu-Cu互连容易存在许多结构缺陷,例如错位,需要对其进行彻底的测试以确保3d - ic的性能。本文详细介绍了局部不对准的原因。然后,利用Matlab工具进行了仿真,最后展示了错位缺陷对电阻和电容参数的影响。
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