M. Goto, J. D. Vos, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, E. Higurashi, Y. Honda, T. Saraya, M. Kobayashi, H. Toshiyoshi, T. Hiramoto
{"title":"Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers","authors":"M. Goto, J. D. Vos, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, E. Higurashi, Y. Honda, T. Saraya, M. Kobayashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/3DIC48104.2019.9058785","DOIUrl":null,"url":null,"abstract":"We report a triple-layering technology for pixelparallel CMOS image sensors. Photodiodes (PDs), logic circuits, and 16-bit pulse counters are developed on silicon-on-insulator (SOI) wafers, and they are three-dimensionally integrated within every pixel by using hybrid bonding through damascened Au electrodes of 5 pm in diameter in a SiO2 insulator. The developed triple-stacked wafers are confirmed to have no voids or separation of layers even after the removal of the handle layer, thereby demonstrating the feasibility of multi-layered imaging devices for the next-generation video systems.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC48104.2019.9058785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We report a triple-layering technology for pixelparallel CMOS image sensors. Photodiodes (PDs), logic circuits, and 16-bit pulse counters are developed on silicon-on-insulator (SOI) wafers, and they are three-dimensionally integrated within every pixel by using hybrid bonding through damascened Au electrodes of 5 pm in diameter in a SiO2 insulator. The developed triple-stacked wafers are confirmed to have no voids or separation of layers even after the removal of the handle layer, thereby demonstrating the feasibility of multi-layered imaging devices for the next-generation video systems.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
