Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Abstract

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on- and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.