Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias

Abstract

In this study, we investigated the temperature cycling reliability of bumpless through silicon vias (TSVs) using a wafer-on-wafer (WOW) process. TSV interconnects were fabricated with and without via bottom cleaning, and TCT tests were conducted under the same conditions. We examined how the cleaning process affected the temperature cycling reliability. In addition, self-aligned multiple TSVs were found to be a key feature of WOW bumpless TSVs. The impact of a multi-via structure on the temperature cycling reliability was investigated as well. The results show that the resistances of bumpless TSVs with via bottom cleaning and multiple TSVs exhibited better temperature cycling reliability.