Transimpedance amplifiers for large-area and ultrahigh bandwidth high-energy particle detectors

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Integration-The Vlsi Journal Pub Date : 2025-02-11 DOI:10.1016/j.vlsi.2025.102382
Jiayi Wang , Yichen Zhang , Yuanjun Guan , Tao Wang , Qianchuan Yi , Wenxin Jiang , Xiaopu Gu , Li Zhang , Binbing Huang , Tianyan Han , Lilei Hu
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Abstract

In the realm of high-energy particle detection, a trade-off exists between achieving a large sensitive area and ensuring high-speed detector response. Current methodologies, such as negative Miller capacitance, have made progress in enhancing both detection area and response speed. Nevertheless, these designs frequently suffer from limitations in parasitic capacitance, especially with large detection areas, which ultimately constrains bandwidth. This study introduces a segmented-integration method combined with optimized front-end circuits to overcome these challenges. By segmenting a single large sensitive area into smaller pixels, each coupled with an independent front-end transimpedance amplifier (TIA), this design can significantly enhance the response speed while maintaining a large sensitive area. Although it complicates the overall system, the output signals from each pixel are summed to preserve the detector's large-area capability. This study has developed novel front-end circuits for both linear and Geiger modes, offering exceptional performance in terms of detector gain and bandwidth. In linear mode, a multi-channel TIA is designed to handle up to 32 pixels simultaneously, providing a gain of 50 dBΩ and 450 MHz bandwidth despite 160 pF parasitic capacitance. For Geiger mode, a novel TIA with a feedforward is proposed, providing a gain of 70 dBΩ and 450 MHz bandwidth for a pixel with a 5 pF parasitic capacitance without the need for compensating capacitors. To enable rapid single-particle counting, a four-delay trigger sampling comparator structure is designed with a sampling rate reaching 4 GS/s under process limitation. The circuits are designed in 180 nm CMOS process and verified through Sentaurus and Cadence simulation software, demonstrating excellent performance with a 68.8 mm2 detection area and an ultrahigh cutoff frequency of 450 MHz.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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